1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of isolation regions and stress regions in a semiconductor structure.
2) Description of the Prior Art
Various techniques have emerged to improve performance of state of the art semiconductors. One technique involves introducing strain. Strained silicon exhibits improved semiconductor performance due to enhanced transport properties. Biaxial distortion of the crystal lattice in strained silicon improves electron and hole mobility.
Another performance enhancement technique involves providing a semiconductor layer separated from the substrate by an insulating layer. Also known as silicon-on-insulator (SOI), such structures exhibit reduced parasitic capacitance, thereby enabling a semiconductor to function at significantly higher speeds with reduced electrical losses. The result is an appreciable increase in performance and a reduction in power consumption.
However, further improvements in device performance are needed to newer technologies.
The importance of improving technology noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The more relevant technical developments in the patent literature can be gleaned by considering the following.
US20050106790A1: Strained silicon on a SiGe on SOI substrate—Inventor: Cheng, Kangguo;
US20050035369A1: Structure and method of forming integrated circuits utilizing strained channel transistors—Inventor: Lin, Chun-Chieh; Hsin-Chu
US20050142700A1: Strained silicon on a SiGe on SOI substrate—Inventor: Cheng, Kangguo;
US20050023616A1: Localized strained semiconductor on insulator—Inventor: Forbes, Leonard;
U.S. Pat. No. 6,251,751: Bulk and strained silicon on insulator using local selective oxidation—Inventor: Chu, Jack Oon;
U.S. Pat. No. 5,232,866: Isolated films using an air dielectric—Inventor: Beyer, Klaus D.